1. Field of the Invention
The present invention relates to a crosstalk verification device for automatically verifying whether or not there is a dangerous portion where crosstalk may occur, for a layout pattern of a designed large scale integrated circuit.
2. Description of the Background Art
In an integrated circuit, since a transistor of low output impedance has a great driving ability, the output waveform on the output line of the transistor becomes abrupt, and as a result, it includes large high frequency components. Thus, such a transistor easily exerts the influence of crosstalk to other line. On the other hand, since a transistor of high output impedance has a poor driving ability, it can not cancel noise well if it appears on its output interconnection line. Thus, such a transistor is easily influenced by the crosstalk from other interconnection line. Conventionally, the designer visually observes to confirm whether or not there is a dangerous portion where the crosstalk may occur for a layout pattern of a designed large scale integrated circuit. That is, the designer, visually searching the layout pattern, identifies the transistor of low output impedance easily exerting influences of crosstalk with the transistor of high output impedance easily influenced by crosstalk in the pattern, and traces the output interconnection line of those transistors, so as to estimate the combination and the place of the output interconnection lines which easily generate the crosstalk.
However, the visual verification of the designer may arise the problem that the designer have to do laborious work. There also arises the problem that some portions where there is a danger of occurrence of crosstalk may sometimes escape the designer's attention.
Further, in view of making integrated circuits larger in scale and making the patterns smaller in future, there is the prospect that with the visual verification by the designers, accurate verification of crosstalk should take place with further difficulty.